1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device in which upper and lower wiring layers are electrically connected to each other through a contact hole formed by a marginless formation technique.
2. Description of the Prior Art
In recent years, the integration scale of integrated circuits (ICs) has been becoming larger and larger through miniaturization of semiconductor device
Now, semiconductor devices with an ultra-large integration scale such as 1-Gigabit (Gb) Dynamic Random-Access Memories (DRAMs) have developed and experimentally fabricated according to the 0.15-.mu.m-order design rule. To cope with such the ultra-large-scale integration of devices, it has been strongly required to eliminate the mask-alignment margin for lithography processes in the fabrication process sequence.
However, the mask-alignment margin has been provided for preventing any problems occurring due to the possible mask-alignment error (i.e., misalignment) during the lithography processes. Therefore, this margin is very difficult to be completely eliminated.
Specifically, in the typical semiconductor device fabrication sequence, a lot of patterned layers, which are usually made of various materials such as metal, semiconductor, dielectric, and so on, are successively formed to be stacked on or over a semiconductor substrate. After a lower patterned layer is formed on or over the substrate, a next, upper layer is formed on the lower patterned layer thus formed. Subsequently, a patterned mask for this upper layer is formed on the upper layer. Then, using this patterned mask, the upper layer is patterned to be aligned with the lower patterned layer by a popular lithography technique.
In this case, it is usually that some placement or overlay error occurs between the upper and lower patterned layers and as a result, a mask-alignment margin is essential for the conventional semiconductor devices. However, this margin will be a cause inhibiting larger-scale integration of devices.
To realize the elimination of the mask-alignment margin, various techniques have been studied and developed, which are termed the "marginless formation techniques".
An important one of the known marginless formation techniques is to eliminate margins for contact holes which are typically formed in an interlayer insulating layer. This marginless formation technique for contact-holes is one of the key measures in view of enhancement of the integration scale and packing density of semiconductor devices, because the contact hole is used for electrically interconnecting a wiring layer with a semiconductor substrate or another wiring layer through an intervening insulating layer.
An important or prevalent one of the known marginless formation techniques for contact holes is termed the "self-aligned contact hole" technique. To realize this technique, concrete structures and/or formation methods have been examined in various ways.
The Japanese Non-Examined Patent Publication No. 4-159725, which was published in June, 1992, discloses a fabrication method of a semiconductor device that realizes the "self-aligned contact hole" technique.
In this conventional method, a pair of insulating sidewall spacers are formed at each side of a gate electrode of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). A contact hole is formed in an interlayer insulating layer covering the MOSFET to reach one of a pair of underlying source/drain regions formed in a semiconductor substrate. The contact hole is self-aligned with the gate electrode.
FIGS. 1A to 1F show the conventional method disclosed in the Japanese Non-Examined Patent Publication No. 4-159725.
First, as shown in FIG. 1A, a patterned field oxide layer 102 is formed on a main surface of a p-type silicon substrate 101 to selectively expose the main surface. A gate oxide layer 103 is formed on the exposed main surface of the substrate 101.
Next, a polycrystalline silicon layer 110 is formed on the field oxide layer 102 and the gate oxide layer 103 over the whole substrate 101 by a Chemical Vapor Deposition (CVD) process. A silicon nitride (SiN.sub.x) layer 105 is formed on the polycrystalline silicon layer 110 over the whole substrate 101 by a CVD process. The state at this stage is shown in FIG. 1A.
Then, the silicon nitride layer 105 and the polycrystalline silicon layer 110 are successively patterned by popular photolithography and Reactive-Ion Etching (RIE) processes. Thus, a gate electrode 104 is formed on the gate oxide layer 103 by the remaining polycrystalline silicon layer 110, and a cap 105a is formed by the remaining silicon nitride layer 105, as shown in FIG. 1B.
Using the gate electrode 104, the cap 105a, and the field oxide layer 102 as a mask, an n-type dopant such as arsenic (As) is selectively ion-implanted into the substrate 101, forming a pair of n-type source/drain regions 106 at each side of the gate electrode 104 in the surface region of the substrate 101. The state at this stage is shown in FIG. 1B.
Then, the uncovered gate oxide layer 103 is removed by using the cap 105a and the gate electrode 104 as a mask. However, this process is not always necessary. In other words, the gate oxide layer 103 may be left in the state shown in FIG. 1B.
Subsequently, a silicon nitride layer 107 is deposited over the whole substrate 101 by a CVD process to cover the MOSFET. The layer 107 is formed on the field oxide layer 102, the exposed substrate 101, the gate electrode 104, and the cap 105a, as shown in FIG. 1C.
The silicon nitride layer 107 is then etched back selectively, thereby forming a pair of sidewall spacers 107a at each side of the gate electrode 104, as shown in FIG. 1D. The bottoms of the sidewall spacers 107a are directly contacted with the substrate 101, i.e., the source/drain regions 106, because the gate oxide layer 103 has been removed.
Following this, a silicon dioxide (SiO.sub.2) layer 10B serving as an interlayer insulating layer is deposited by a CVD process over the whole substrate 101, covering the MOSFET, as shown in FIG. 1E.
A photoresist film 111 with a window 112 is formed on the interlayer insulating layer 108 thus deposited. As shown in FIG. 1E, an end of the window 112 is overlapped with a corresponding one of the pair of sidewall spacers 107a.
Using the photoresist film 111 as a mask, the interlayer insulating layer 108 is selectively etched by a wet etching process using buffered hydrogen fluoride (HF) Thus, a contact hole 108a is formed in the interlayer insulating layer 108 at a corresponding position to the window 112. The contact hole 108a uncovers a corresponding one of the pair of source/drain regions 106.
If the gate oxide layer 103 is not removed in the step in FIG. 1C, the gate oxide layer 103 is selectively etched during the etching process for the interlayer insulating layer 108.
After removing the photoresist film 111, a patterned wiring layer 109 is formed on the interlayer insulating layer 108 by popular processes. The wiring layer 109 is contacted with and electrically connected to the corresponding one of the source/drain regions 106 through the contact hole 108a of the interlayer insulating layer 108. The state at this stage is shown in FIG. 1F.
Another structure realizing the "self-aligned contact hole" technique was disclosed by T. Yamada et al. in the technical digest, pp. 35-38, 1989 International Electron Devices Meeting (IEDM), published in 1989.
In this conventional structure, a conductive layer is selectively grown on a source/drain region in self-alignment with a gate electrode using insulating sidewall spacers and a field oxide layer. An interlayer insulating layer formed to cover the selectively-grown conductive layer. A contact hole is formed in the interlayer insulating layer to extend the underlying conductive layer.
FIG. 2 shows the conventional semiconductor device disclosed in the 1989 IEDM technical digest.
A field oxide layer 122 is selectively formed on a main surface of a p-type silicon substrate 121. Gate electrodes 124 for MOSFETs are formed on the uncovered main surface of the substrate 121 through gate oxide layers 123, respectively. Silicon dioxide caps 125 are formed on the top faces of the gate electrodes 124, respectively. Pairs of insulating sidewall spacers 126 are formed at each side of the gate electrodes 124, respectively. Pairs of n-type source/drain regions 127 for the MOSFETs are formed in the surface region of the substrate 121 in self-alignment with the gate electrodes 124 and the sidewall spacers 126, respectively.
Silicon layers 128 are selectively grown on the exposed main surface of the substrate 121 between the sidewall spacers 126 and the opposing field oxide layer 122, respectively. The silicon layers 128 are doped with a dopant by ion-implantation to decrease their electric resistance. The tops of the silicon layers 128 are higher than the tops of the caps 125. One ends of the silicon layers 128 are located on the field oxide layer 122 to be overlapped therewith. The other ends of the silicon layers 128 are located on the corresponding silicon dioxide caps 125 to be overlapped therewith.
An interlayer insulating layer 129 is formed to cover the MOSFETs, the silicon layers 128, and the exposed filed oxide layer 122. Contact holes 129a are formed in the layer 129 to extend the corresponding silicon layers 128.
Wiring layers 130 are formed on the interlayer insulating layer 129 to be contacted with the silicon layers 128 through the corresponding contact holes 129a, respectively.
With the conventional method disclosed in the Japanese Non-Examined Patent Publication No. 4-159725, as shown in FIGS. 1A to 1F, the top and side faces of the gate electrode 104 are covered with silicon nitride cap 105a and the silicon nitride spacers 107a, respectively. Therefore, the contact hole 108a of the interlayer insulating layer 108 is formed in self-alignment with the gate electrode 104 without any margin. However, this method has the following two problems.
A first problem is that a large parasitic capacitance tends to occur in the vicinity of the contact hole 108a. This is because the gate electrode 104 and the wiring layer 109 are separated or electrically insulated by the silicon nitride spacer 107a with a relatively large dielectric constant in the vicinity of the contact hole 108a. This large parasitic capacitance will give a bad effect to high speed operation of the semiconductor device.
A second problem is that the hot-carrier resistance tends to degrade, resulting in deterioration in long-term reliability of the MOSFET. This problem is caused by the following reason.
As seen from FIG. 1F, the bottoms of the silicon nitride spacers 107a are directly contacted with the n-type source/drain regions 106, respectively. Therefore, hot carriers generated in one of the source/drain regions 106 that serves as a drain region tend to be trapped by a corresponding one of the spacers 107a. As a result, the electrical characteristics of the MOSFET such as the threshold voltage tend to fluctuate or deviate with time. This means that the hot-carrier resistance tends to degrade.
This phenomenon was reported by T. Mizuno et al. in the 1988 IEDM technical digest, pp. 234-237, published in 1988.
With the conventional structure disclosed in the 1989 IEDM technical digest, as seen from FIG. 2, the top and side faces of the gate electrode 124 are covered with the silicon dioxide cap layer 125 and the silicon dioxide spacers 126, respectively. Silicon dioxide has a smaller dielectric constant than that of silicon nitride. Therefore, the above first problem about the parasitic capacitance in the conventional method disclosed in the Japanese Non-Examined Patent Publication No. 4-159725 is solved.
Moreover, the sidewall spacers 126 are located on the corresponding gate oxide layer 123 and as a result, the above second problem about the long-term reliability in the conventional method disclosed in the Japanese Non-Examined Patent Publication No. 4-159725 is solved.
However, the structure in FIG. 2 has another problem relating to electrical insulation between the cap layer 125 and the selectively-grown silicon layer 128.
Specifically, when the contact holes 129a are formed in the interlayer insulating layer 129 by an etching process, the contact holes 129a may be located with some lateral shift with respect to the silicon layers 128 and as a result, they may be close to or contacted with the corresponding silicon-dioxide caps 125 due to mask-alignment error. If the contact holes 129a are close to the corresponding silicon-dioxide cap layers 125, leakage-current increase or short-circuit tends to occur between the wiring layers 130 and the corresponding gate electrodes 124. If the contact holes 129a are contacted with the corresponding silicon-dioxide caps 125, short-circuit will occur between the wiring layers 130 and the corresponding gate electrodes 124.
To prevent these disadvantages, it is necessary for the contact holes 129a not to be contacted or overlapped with the corresponding caps 125. In other words, the overlapped length 131 of each selectively-grown silicon layer 128 with the corresponding cap 125 needs to be longer than the alignment margin 133 of the corresponding silicon layer 128.
However, if the overlapped length 131 of the selectively-grown silicon layer 128 is designed to be longer than the alignment margin 133, the gap or space 132 between the opposing ends of the adjoining two silicon layers 128 becomes narrow. This leads to leakage current increase or short-circuit between these two layers 128 or the adjoining two wiring layers 130.
Thus, the electrical insulation between the wiring layers 130 and the corresponding gate electrodes 124 is a trade-off for the electrical insulation between the adjoining silicon layers 128 or the wiring layers 130. This means that it is difficult for the conventional structure disclosed in FIG. 2 to miniaturize the semiconductor device to thereby increase its packing density.
For example, for 1-Gb DRAMS designed with the 0.15-.mu.m rule, it is typical that the width of gate electrode 124 (i.e., the gate length) is set as approximately 0.15 .mu.m (150 nm), and that the alignment margin 133 for the contact holes 129a is set as approximately 0.05 .mu.m (50 nm). As a result, if priority is given to the electrical insulation between the wiring layers 130 and the corresponding gate electrodes 124, the space 132 of the selective-grown silicon layers 128 will be designed as a value less than 0.05 .mu.m (50 nm).